To address design verification problems with complex mixed-signal systems-on-chip (SoCs), Siemens has introduced the Symphony Pro platform for automotive, imaging, IoT, 5G, computing and storage applications.

This extends the mixed-signal verification capabilities of Siemens’ proven Symphony platform to support Accellera standardised verification methodologies with an intuitive visual debug cockpit, resulting in productivity improvements of up to ten times.

Automotive, imaging, IoT, 5G, computing and storage applications are driving strong demand for greater analogue and mixed-signal content in SoCs. Mixed-signal circuits are increasingly ubiquitous, whether it is integrating the analogue signal chain with the digital-front end (DFE) in 5G massive-MIMO radios, digital RF-sampling data converters in radar systems, image sensors combining analogue pixel read-out circuits with digital image signal processing or feeding data-centre computing resources with more data using mixed-signal circuits to deliver PAM4 signalling. Mixed-signal circuits enable lower power, area and cost while delivering improving performance figures.

“Mixed-signal functional verification is increasingly vital for our sophisticated designs targeted for the imaging and automotive industries,” said Stephane Vivien, senior CAD manager at ST Microelectronics. “We’ve participated in the early access programme for Symphony Pro and have seen significant productivity gains thanks to advanced debugging capabilities and seamless support for multi-layer sandwich configurations in Symphony Pro. We look forward to using Symphony Pro as our sign-off for present and future mixed-signal verification projects.”

Increased application of digital control, digital calibration and digital signal processing techniques in modern mixed-signal chip architectures is driving a shift in mixed-signal verification methodologies towards more digital-centric approaches. The Symphony Pro platform – built on the performance of Siemens’ Symphony and Questa Visualizer platforms – extends the rapid deployment of standard universal verification methodology (UVM) and unified power format (UPF) driven low-power techniques into the mixed signal domain by offering fast simulation performance in a unified environment for better throughput and capacity.

Modern mixed-signal SoCs integrate analogue circuits with logic gates operating at very high clock speeds. This high frequency bi-directional signal flow at the boundary of analogue and digital pushes the limit of manual debug methodologies impacting the overall time to results. The Symphony Pro Visualizer MS environment offers a seamless debug experience across the entire mixed-signal design hierarchy with analysis, automation and ease-of-use for increased productivity.

“Our high-performance, energy-efficient chips designed for the IoT are analogue intensive and mixed-signal in nature,” said Jayanth Shreedhara, senior CAD manager at Silicon Labs. “To ensure high quality, we expanded our digital verification methodology to enable effective regression of our mixed-signal designs. Symphony Pro Visualizer mixed-signal technology accelerated debug turn-around time for our digital on top UVM test suites, enhancing our verification productivity from days to hours and dramatically improving our coverage closure.”

Ravi Subramanian, senior vice president at Siemens Digital Industries Software, added: “Our customers are rapidly advancing the state-of-the-art in mixed-signal SoC design across a wide range of applications and, in the process, they are driving the requirements for new innovations in the EDA tools required to design, verify and validate these chips. We are excited to deliver Symphony Pro, which combines our proven AFS, Questa and Visualizer technologies, to our customers, enabling the potential for them to realise key competitive advantages with unified mixed-signal verification.”